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Weixin Official Accounts Platform AURIX TC4x CDSP Introduction and Application Original Cobb Song Infineon Automotive Electronics Ecosystem Infineon Automotive Electronics Ecosystem Infineon Technologies (China) Co., Ltd. Infineon has over forty years of rich experience and technical accumulation in automotive semiconductors, dedicated to achieving clean, safe, and intelligent cars with microelectronics. The Infineon Automotive Electronics Ecosystem shares with you the latest technologies, products, solutions, collaborations, and trends in Infineon automotive electronics, building a platform for technical exchange and market cooperation with local partners. 131 original contents July 30, 2024 07:03 Shanghai Infineon MCU AURIX Review AURIX TC4x Introduction to the Parallel Processing Unit (PPU) AURIX TC4x Free Development Environment Introduction Infineon’s New Generation MCU AURIX TC4x Soon to be Mass Produced From Origin to Present: Infineon Automotive Grade MCU Fully Supports Rust Language Development Exploring AUTOSAR and Infineon AURIX TC4x MCAL Solution – Part 1 Exploring AUTOSAR and Infineon AURIX TC4x MCAL Solution – Part 2 AURIX TC4x Virtualization Technology Aids Next-Generation Automotive EE Architecture Design In-Vehicle Ethernet and AURIX TC4x Gigabit Ethernet/Time-Sensitive Network Overview AURIX TC4x Network Security Architecture and Support for ISO/SAE 21434 Functional Safety Best Partner: AURIX TC4x and OPTIREG PMIC Overview of TLF4x Functional Safety Introduction Infineon’s AURIX TC4x Microcontroller CDSP – Converter Digital Signal Processor is specifically designed for high-performance programmable digital signal processing and control units. Its core is the Synopsys DesignWare ARC EM5D (ARC) 32-bit processor. The CDSP is used for post-processing signals from Delta-Sigma ADC (DSADC), external modulators (EXMOD), time-division multiplexing ADC (TMADC), carrier amplitude (CARMAG), or general-purpose registers (GP), etc. The CDSP module provides a rich set of ARC core CPU instructions, supporting various algorithms and data types, including floating-point, fixed-point, complex numbers, etc., and can be widely used in audio, video, communication, and other digital signal processing fields. 1 Introduction to CDSP Architecture Figure 1 TC4x Microcontroller Schematic Diagram Figure 1 TC4x Microcontroller Schematic, where the CDSP is located in the ADC module and can quickly achieve data exchange and communication with the PPU through the LLI low-latency bus; it can also communicate through the CPB converter peripheral bus to simultaneously transmit multiple data bits, improving data transmission speed and efficiency. The main modules and functions of the CDSP core architecture are as follows: Core Architecture: Synopsys ARC v2 DSP Core EM5D Using Harvard architecture processor with three-level reduced instruction set computing (RISC) pipeline technology A 32×32 single-cycle multiply-accumulate (MAC) unit for efficient digital signal processing One master port for acquiring analog-to-digital converter (ADC) results and writing results into the result FIFO buffer With 2 slave interfaces for external master device access to instructions and data memory With 3KB of instruction cache ICCM and 3KB of data cache DCCM Instruction set architecture focused on digital signal processing Clock frequency of 160MHz Independent processor input interfaces DSADC internal result registers EXMOD internal result registers DSADC carrier generator carrier amplitude value (CARMAG) TMADC internal result registers 4 general-purpose registers Write access to program RAM and data RAM through FPI bus system Output interface of each processor Main result output register (RES0) with depth 4 FIFO 2 auxiliary result registers Read access to data RAM through FPI bus system Event signal (service request generation) Result generation (configured according to FIFO fill level in FIFO mode) Timestamp generation Limit check conditions (signal within or out of range) Processor state (processor wake-up error, system has stopped) Etc., for detailed information, refer to the manual. 2 CDSP Features and Performance CDSP operating frequency: 160 MHz Processing power: 18 x CDSP: 18 x 289 DMIPS (two CDSP cores equivalent to one Trcore processing power) The CDSP usually processes input signals from DSADC, EXMOD, TMADC, GP, CARMAG, etc., and can flexibly implement their filtering algorithms in software, as shown in Figure 2: Figure 2 Filter Function TC2x/3x Hardware Implementation to TC4x CDSP Software Implementation Users can self-program the Infineon CDSP to implement FIR, IIR, DA, MAT, Luenberger Observer, and other filtering algorithms. Infineon also provides corresponding commercial library file filter functions. For example: Fast Fourier Transform FFT, Luenberger Observer, multi-channel averaging, etc. Figure 3 Model Development Supported Toolchain Simulink model support. Infineon provides software routines, allowing users to generate software code and algorithms through MATLAB models, thereby quickly deploying them, greatly simplifying development difficulty, and speeding up user development. Refer to schematic diagram 3: 3 CDSP safety Hardware safety concepts primarily rely on redundancy. In safety design, redundancy is an important mechanism for improving system reliability and safety. CDSP software is part of hardware functional safety cases, without a dedicated functional safety plan. CDSP is certified for ASIL-D level process certification and functional certification (hardware + software), including timing requirements. TC4x MCAL is certified for ASPICE version 3.1 ASPICE L3 process, compliant with ISO 26262 2nd edition, ISO 21434, and MISRA standards. 4 CDSP Application Scenarios Compatible with traditional internal combustion engine applications, digital filter module configuration for knock detection: The output voltage of the knock sensor is converted into bitstream signals by the internal DS modulator. The bitstream is connected to three CDSPs with SW filter chains, each instance being configured with the corresponding band-pass characteristics (fB1, fB2, fB3). Based on the internal rectifier and integrator function of the digital filter chain, the knock intensity of each bandwidth (fB1, fB2, fB3) is calculated. The system framework diagram is referenced in schematic diagram 4: Figure 4 CDSP implements knock detection3 CDSP safety: The hardware safety concept mainly depends on redundancy. In safety design, redundancy is an important mechanism used to improve the reliability and safety of the system. The CDSP software is part of the hardware functional safety case and does not have a dedicated functional safety plan. CDSP is certified for ASIL-D level process certification and functional certification (hardware + software), which includes timing requirements. TC4x MCAL complies with ASPICE version 3.1 ASPICE L3 process certification and complies with ISO 26262 Second Edition, ISO 21434, and MISRA standards. 4 CDSP application scenarios: Compatible with traditional internal combustion engine applications, digital filter module configuration for knock detection: The output voltage of the knock sensor is converted into a bitstream signal by the internal DS modulator. The bitstream is connected to the three CDSPs with SW filter chains, where each instance is configured with the corresponding bandpass characteristics (fB1, fB2, fB3). Based on the internal rectifier and integrator functions of the digital filter chain, the knock intensity in each bandwidth (fB1, fB2, fB3) is calculated. The system framework diagram is referred to in Schematic 4: Figure 4 CDSP Implementation of Knock Detection In xEV Inverter applications, CDSP implements average current detection and Luenberger observer, achieving efficient and cost-effective resolver decoding functions. Through 3 DSADC channel measurements, CDSP software post-processing achieves motor average current measurement; using 2 DSADC channels measurement, inputs CDSP to achieve Luenberger observer calculation speed and position information. The Luenberger observer can provide accurate angle information, support higher motor speeds, improve efficiency, and reduce costs. The system framework diagram is referred to in Schematic 5: Figure 5 CDSP Implementation of Average Current Detection and Luenberger Observer Architecture Schematic Suitable for sensorless motor control of small motors